The semiconductor industry produces vast quantities of semiconductor wafers; i.e., thin slices of a semiconductive material used as a base for an electronic component or integrated circuit. Each wafer typically includes a flat, highly-polished surface critical for formation of the integrated circuit, and, by extension, performance of the semiconductor. Therefore, the geometry and quality of the wafer surface are absolute prerequisites to product performance in this field of endeavor. To achieve optimal surface conditions for circuit formation, wafers are polished. Generally, this is accomplished with a polishing machine, models of which are known in the art.
For example, many models of the prior and current art provide machines having one or more polishing units with heads that accommodate wafers. Wafer loading mechanisms (WLM) load and unload a wafer into and from the head portion of the polishing unit during various processing steps of a single processing cycle. Once the head of the polishing unit is loaded with a wafer, the polishing unit translates along or around a column until positioned over a rotating platen. The polishing unit vertically descends towards the platen and load forces act to hold a surface of the wafer sovereign to the platen. Thereafter, the machinery components act in concert to polish the wafer surface, producing an end product. There are many polishing machines in the industry that frequently load and unload wafers between polishing processes in multistep polishing. An example of this type of machine is disclosed in the U.S. Pat. No. 5,830,045 to Togawa, et al. which discloses a polishing apparatus that polishes a workpiece such as a semiconductor wafer to a flat mirror finish.
There is second group of machines that avoid undesirable multiple loading and unloading of the fragile wafers. These machines are generally perceived in the industry to be more reliable in operation. An example of this type of machine is disclosed in the U.S. Pat. No. 6,050,885 to Morsch, et al., which discloses a device for the chemical-mechanical polishing of the surface of an object, in particular of the semiconductor wafers for the manufacture of semiconductors, with two polishing units with height-adjustable vacuum holders each for a semiconductor wafer. This machine design is linear in configuration, compact, reliable, easy access for service; however, this linear design has the disadvantage of low throughput.
Successive, linear processing sequences are gated by predecessor sequences, due to the constraint of processing along a single axis, and result in less than optimal throughput. Even in systems having more than one linear processing path (e.g., two platens, two linear guides above the centers of the platens and with two polishing units on different sides of linear guides moving independently in linear fashion on each of two predetermined parallel paths), the number of paths is mechanically limited to just a two, and the number of independent polishing units on each side of the guide assembly is restricted to just one. Each process on each path remains limited by predecessor processes. Thus attempts to increase throughput for this linear design have not been entirely successful (see FIG. 1, with linear path depicted at 2). Another example of this type of machine with single load and unload operation for wafer in multistep processing is the U.S. Pat. No. 5,738,574 to Tolles, et al. (refer to FIGS. 2 and 3; a circular processing path is depicted in FIG. 3 at 4). This machine has high throughput because there are generally three polishing units doing polishing on three platens of the machine. But this machine is less compact and more difficult for service than machine of the previous example and less flexible in formulating polishing processes than polishing machines of the first type.
While it is known in the art that a wafer tends to remain intact if it is securely positioned in the head of the polishing unit, the head of the polishing unit is able to provide protection for the wafer only during the time in which the wafer is actually secured in the head. Further, the systems of the prior art are entirely reliant on a mechanical symbiosis between the head and the polishing unit. This unity of structure is required in the prior art due to the complex network of conduits, valves, chambers and gauges constructed to integrally span both the polishing unit and its head. Thus the prior art head can only be removed from its associated polishing unit on an exceptional basis; e.g., emergency maintenance. Such removal is a time-consuming, labor-intensive manual process that halts normal polishing operations until such maintenance can be completed. Additionally, the interdependency between the prior art polishing unit and its head restrict the throughput, as the head is dependent on its associated polishing unit, and the path of the polishing unit is gated by predecessor polishing units, load and unload processes and the like (refer to FIG. 4, where a polish unit 6 of the prior art and having an integral head 8 and a complex network of conduits 9 integrally distributed throughout the entire polish unit 6 and its integral head 8 is shown).
Examples of such art include the U.S. Pat. No. 6,113,480 to Hu, et al. that discloses a semi-conductor wafer polishing head that includes, inter alia, three air lines, an air control system, including air line pressure checking and chamber leak rate testing, valves, and a pair of air gauges. The U.S. Pat. No. 5,587,899 to Volodarsky, et al. discloses a polishing head for polishing a semiconductor wafer that includes a source of pressurized fluid, vacuum source, valve, adjustable pressure regulator, a first fluid conduit and a second fluid conduit. The U.S. Pat. Nos. 6,024,630 to Shendon, et al., 5,527,209 to Volodarsky, et al., 6,210,260 B1 to Tanaka et al., 5,205,082 to Shendon, et al., and 5,738,574 to Tolles, et al. all disclose similar inventions.
What is needed, then, is an efficient, low-cost apparatus and method for polishing wafers that enable multiple, contemporaneous yet diverse processes cycles, accommodate variable configurations of platens, polishing units, and heads for high throughput. Additionally, such a system and method must provide protection for wafers during all phases of processing to conserve work material and promote efficient processing. It is also desirable to provide the same in a compact construct compatible with various work environments, customer budgets and customer processing needs.